High density integrated circuit apparatus, test probe and methods of use thereof

ABSTRACT

The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed ion the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.

FIELD OF THE INVENTION

This invention relates to an apparatus and test probe for integratedcircuit devices and methods of use thereof.

BACKGROUND OF THE INVENTION

In the microelectronics industry, before integrated circuit (IC) chipsare packaged in an electronic component, such as a computer, they aretested. Testing is essential to determine whether the integratedcircuit's electrical characteristics conform to the specifications towhich they were designed to ensure that electronic component performsthe function for which it was designed.

Testing is an expensive part of the fabrication process of contemporarycomputing systems. The functionality of every I/O for contemporaryintegrated circuit must be tested since a failure to achieve the designspecification at a single I/O can render an integrated circuit unusablefor a specific application. The testing is commonly done both at roomtemperature and at elevated temperatures to test functionality and atelevated temperatures with forced voltages and currents to burn thechips in and to test the reliability of the integrated circuit to screenout early failures.

Contemporary probes for integrated circuits are expensive to fabricateand are easily damaged. Contemporary test probes are typicallyfabricated on a support substrate from groups of elongated metalconductors which fan inwardly towards a central location where eachconductor has an end which corresponds to a contact location on theintegrated circuit chip to be tested. The metal conductors generallycantilever over an aperture in the support substrate. The wires aregenerally fragile and easily damage and are easily displaceable from thepredetermined positions corresponding to the design positions of thecontact locations on the integrated circuit being tested. These probeslast only a certain number of testing operations, after which they mustbe replaced by an expensive replacement or reworked to recondition theprobes.

FIG. 1 shows a side cross-sectional view of a prior art probe assembly 2for probing integrated circuit chip 4 which is disposed on surface 6 ofsupport member 8 for integrated circuit chip 4. Probe assembly 2consists of a dielectric substrate 10 having a central aperture 12therethrough. On surface 14 of substrate 10 there are disposed aplurality of electrically conducting beams which extend towards edge 18of aperture 12. Conductors 16 have ends 20 which bend downwardly in adirection generally perpendicular to the plane of surface 14 ofsubstrate 10. Tips 22 of downwardly projecting electrically conductingends 20 are disposed in electrical contact with contact locations 24 onsurface 25 of integrated circuit chip 4. Coaxial cables 26 bringelectrical signals, power and ground through electrical connectors 28 atperiphery 30 of substrate 10. Structure 2 of FIG. 1 has the disadvantageof being expensive to fabricate and of having fragile inner ends 20 ofelectrical conductors 16. Ends 20 are easily damaged through use inprobing electronic devices. Since the probe 2 is expensive to fabricatereplacement adds a substantial cost to the testing of integrated circuitdevices. Conductors 16 were generally made of a high strength metal suchas tungsten to resist damage from use. Tungsten has an undesirably highresistivity.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an improved highdensity test probe, test apparatus and method of use thereof.

It is another object of the present invention to provide an improvedtest probe for testing and burning-in integrated circuits.

It is another object of the present invention to provide an improvedtest probe and apparatus for testing integrated circuits in wafer formand as discrete integrated circuit chips.

It is an additional object of the present invention to provide probeshaving contacts which can be designed for high performance functionaltesting and for high temperature burn in applications.

It is yet another object of the present invention to provide probeshaving contacts which can be reworked several times by resurfacing someof the materials used to fabricate the probe of the present invention.

It is a further object of the present invention to provide an improvedtest probe having a probe tip member containing a plurality of elongatedconductors each ball bonded to electrical contact locations on spacetransformation substrate.

A broad aspect of the present invention is a test probe having aplurality of electrically conducting elongated members embedded in amaterial. One end of each conductor is arranged for alignment withcontact locations on a workpiece to be tested.

In a more particular aspect of the present invention, the other end ofthe elongated conductors are electrically connected to contact locationson the surface of a fan-out substrate. The fan-out substrate providesspace transformation of the closely spaced electrical contacts on thefirst side of the fan-out substrate. Contact locations having a largerspacing are on a second side of the fan out substrate.

In yet another more particular aspect of the present invention, pins areelectrically connected to the contact locations on the second surface ofthe fan out substrate.

In another more particular aspect of the present invention, theplurality of pins on the second surface of the fan-out substrate areinserted into a socket on a second fan-out substrate. The first andsecond space transformation substrates provide fan out from the finepitch of the integrated circuit I/O to a larger pitch of electricalcontacts for providing signal, power and ground to the workpiece to betested.

In another more particular aspect of the present invention, the pin andsocket assembly is replaced by an interposer containing a plurality ofelongated electrical connectors embedded in a layer of material which issqueezed between contact locations on the first fan- out substrate andcontact locations on the second fan-out substrate.

In another more particular aspect of the present invention, the testprobe is part of a test apparatus and test tool.

Another broad aspect of the present invention is a method of fabricatingthe probe tip of the probe according to the present invention wherein aplurality of elongated conductors are bonded to contact locations on asubstrate surface and project away therefrom.

In a more particular aspect of the method according to the presentinvention, the elongated conductors are wire bonded to contact locationson the substrate surface. The wires project preferably at anonorthogonal angle from the contact locations.

In another more particular aspect of the method of the presentinvention, the wires are bonded to the contact locations on thesubstrate are embedded in a elastomeric material to form a probe tip forthe structure of the present invention.

In another more particular aspect of the present invention, theelongated conductors are embedded in an elastomeric material.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-section of a conventional test probe for anintegrated circuit device.

FIG. 2 is a schematic diagram of one embodiment of the probe structureof the present invention.

FIG. 3 is a schematic diagram of another embodiment of the probestructure of the present invention.

FIG. 4 is an enlarged view of an elastomeric connector electricallyinterconnecting two space transformation substrates of the structure ofFIG. 2.

FIG. 5 is an enlarged view of the probe tip within dashed circle 100 ofFIGS. 2 or 3.

FIG. 6 shows the probe tip of the structure of FIG. 5 probing anintegrated circuit device.

FIGS. 7-13 show the process for making the structure of FIG. 5.

FIG. 14 shows a probe tip structure without a fan-out substrate.

FIG. 15 shows the elongated conductors of the probe tip fixed by solderprotuberances to contact locations on a space transformation substrate.

FIG. 16 shows the elongated conductors of the probe tip fixed by laserweld protuberances to contact locations on a space transformationsubstrate.

FIG. 17 shows both interposer 76 and probe tip 40 rigidly bonded tospace transformer 60.

DETAILED DESCRIPTION

Turning now to the figures, FIGS. 2 and 3 show two embodiments of thetest assembly according to the present invention. Numerals commonbetween FIGS. 2 and 3 represent the same thing. Probe head 40 is formedfrom a plurality of elongated electrically conducting members 42embedded in a material 44 which is preferably an elastomeric material44. The elongated conducting members 42 have ends 46 for probing contactlocations on integrated circuit devices 48 of wafer 50. In the preferredembodiment, the workpiece is an integrated circuit such as asemiconductor chip or a semiconductor wafer having a plurality of chips.The workpiece can be any other electronic device. The opposite ends 52of elongated electrical conductors 42 are in electrical contact withspace transformer (or fan-out substrate) 54. In the preferredembodiment, space transformer 54 is a multilevel metal/ceramicsubstrate, a multilevel metal/polymer substrate or a printed circuitboard which are typically used as packaging substrates for integratedcircuit chips. Space transformer 54 has, in the preferred embodiment, asurface layer 56 comprising a plurality of thin dielectric films,preferably polymer films such as polyimide, and a plurality of layers ofelectrical conductors, for example, copper conductors. A process forfabricating multilayer structure 56 for disposing it on surface 58 ofsubstrate 60 to form a space transformer 54 is described in U.S. patentapplication Ser. No. 07/695,368, filed on May 3, 1991, entitled“MULTI-LAYER THIN FILM STRUCTURE AND PARALLEL PROCESSING METHOD FORFABRICATING SAME” which is assigned to the assignee of the presentinvention, the teaching of which is incorporated herein by reference.Details of the fabrication of probe head 40 and of the assembly of probehead 40 and 54 will be described herein below.

As sown in FIG. 2, on surface 62 of substrate 60, there are, a pluralityof pins 64. Surface 62 is opposite the surface 57 on which probe head 40is disposed. Pins 64 are standard pins used on integrated circuit chippackaging substrates. Pins 64 are inserted into socket 66 or platedthrough-holes in the substrate 68 which is disposed on surface 70 ofsecond space transformer 68. Socket 66 is a type of pin grid array (PGA)socket such as commonly disposed on a printed circuit board of anelectronic computer for receiving pins from a packaging substrate.Second space transformer 68 can be any second level integrated circuitpackaging substrate, for example, a standard printed circuit board.Socket 66 is disposed on surface 70 of substrate 68. On opposite surface70 of substrate 68 there are disposed a plurality of electricalconnectors to which coaxial cables 72 are electrically connected.Alternatively, socket 68 can be a zero insertion force (ZIF) connectoror the socket 68 can be replaced by through-holes in the substrate 68wherein the through-holes have electrically conductive materialsurrounding the sidewalls such as a plated through-hole.

In the embodiment of FIG. 3, the pin 64 and socket 66 combination of theembodiment of FIG. 2 is replaced by an interposer, such as, elastomericconnector 76. The structure of elastomeric connector 76 and the processfor fabricating elastomeric connector 76 is described in copending U.S.patent application Ser. No. 07/963,364 to B. Beaman et al., filed Oct.19, 1992, entitled “THREE DIMENSIONAL HIGH PERFORMANCE INTERCONNECTIONMEANS”, which is assigned to the assignee of the present invention, theteaching of which is incorporated herein by reference and of which thepresent application is a continuation-in-part thereof, the priority dateof the filing thereof being claimed herein. The elastomeric connectorcan be opted to have one end permanently bonded to the substrate, thusforming a FRU (field replacement unit) together with theprobe/substrate/connector assembly.

FIG. 4 shows a cross-sectional view of structure of the elastomericconnector 76 of FIG. 3. Connector 76 is fabricated of preferablyelastomeric material 78 having opposing, substantially parallel andplanar surfaces 80 and 82. Through elastomeric material 78, extendingfrom surface 81 to 83 there are a plurality of elongated electricalconductors 85. Elongated electrical conductors 84 are preferably at anonorthogonal angle to surfaces 81 and 83. Elongated conductors 85 arepreferably wires which have protuberances 86 at surface 81 ofelastomeric material layer 78 and flattened protuberances 88 at surface83 of elastomeric material layer 78. Flattened protuberances 88preferably have a projection on the flattened surface as shown for thestructure of FIG. 14. Protuberance 86 is preferably spherical andflattened protuberance 88 is preferably a flattened sphere. Connector 76is squeezed between surface 62 of substrate 54 and surface 73 ofsubstrate 68 to provide electrical connection between end 88 of wires 85and contact location 75 on surface 73 of substrate 68 and between end 88or wires 85 and contact location 64 on surface 62 of substrate 54.

Alternatively, as shown in FIG. 17, connector 76 can be rigidly attachedto substrate 54 by solder bonding ends 88 of wires 85 to pads 64 onsubstrate 54 or by wire bonding ends 86 of wires 85 to pads 64 onsubstrate 54 in the same manner that wires 42 are bonded to pads 106 asdescribed herein below with respect to FIG. 5. Wires 85 can be encasedin an elastomeric material in the same manner as wires 42 of FIG. 5.

Space transformer 54 is held in place with respect to second spacetransformer 68 by clamping arrangement 80 which is comprised of member82 which is perpendicularly disposed with respect to surface 70 ofsecond space transformer 68 and member 84 which is preferably parallelydisposed with respect to surface 86 of first space transformer 54.Member 84 presses against surface 87 of space transformer 54 to holdspace transformer 54 in place with respect surface 70 of spacetransformer 64. Member 82 of clamping arrangement 80 can be held inplace with respect to surface 70 by a screw which is inserted throughmember 84 at location 90 extending through the center of member 82 andscrew into surface 70.

The entire assembly of second space transformer 68 and first spacetransformer with probe head 40 is held in place with respect wafer 50 byassembly holder 94 which is part of an integrated circuit test tool orapparatus. Members 82, 84 and 90 can be made from materials such asaluminum.

FIG. 5 is a enlarged view of the region of FIGS. 2 or 3 closed in dashedcircle 100 which shows the attachment of probe head 40 to substrate 60of space transformer 54. In the preferred embodiment, elongatedconductors 42 are preferably wires which are at a non-orthogonal anglewith respect to surface 87 of substrate 60. At end 102 of wire 42 thereis preferably a flattended protuberance 104 which is bonded (by wirebonding, solder bonding or any other known bonding technique) toelectrically conducting pad 106 on surface 87 of substrate 60.Elastomeric material 44 is substantially flush against surface 87. Atsubstantially oppositely disposed planar surface 108 elongatedelectrically conducting members 42 have an end 110. In the vicinity ofend 110, there is optimally a cavity 112 surrounding end 110. The cavityis at surface 108 in the elastomeric material 44.

FIG. 6 shows the structure of FIG. 5 used to probe integrated circuitchip 114 which has a plurality of contact locations 116 shown as spheressuch as a C4 solder balls. The ends 110 of conductors 42 are pressed incontact with contact locations 116 for the purpose of electricallyprobing inteprated circuit 114. Cavity 112 provides an opening inelastomeric material 44 to permit ends 110 to be pressed towards andinto solder mounds 116. Cavity 112 provides a means for solder mounds116 to self align to ends 110 and provides a means containing soldermounds which may melt, seep or be less viscous when the probe isoperated at an elevated temperature. When the probe is used to test orburn-in workpieces have flat pads as contact locations the cavities 112can remain or be eliminated.

FIGS. 7-13 show the process for fabricating the structure of FIG. 5.Substrate 60 with contact locations 106 thereon is disposed in a wirebond tool. The top surface 122 of pad 106 is coated by a method such asevaporation, sputtering or plating with soft gold or Ni/Au to provide asuitable surface for thermosonic ball bonding. Other bonding techniquescan be used such as thermal compression bonding, ultrasonic bonding,laser bonding and the like. A commonly used automatic wire bonder ismodified to ball bond gold, gold alloy, copper, copper alloy, aluminum,Pt, nickel or palladium wires 120 to the pad 106 on surface 122 as shownin FIG. 7. The wire preferably has a diameter of 0.001 to 0.005 inches.If a metal other than Au is used, a thin passivation metal such as Au,Cr, Co, Ni or Pd can be coated over the wire by means of electroplating,or electroless plating, sputtering, c-beam evaporation or any othercoating techniques known in the industry. Structure 124 of FIG. 7 is theball bonding head which has a wire 126 being fed from a reservoir ofwire as in a conventional wire bonding apparatus. FIG. 7 shows the ballbond head 124 in contact at location 126 with surface 122 of pad 106.

FIG. 8 shows the ball bonding head 124 withdrawn in the directionindicated by arrow 128 from the pad 106 and the wire 126 drawn out toleave disposed on the pad 106 surface 122 wire 130. In the preferredembodiment, the bond head 124 is stationary and the substrate 60 isadvanced as indicated by arrow 132. The bond wire is positioned at anangle preferably between 5 to 60° from vertical and then mechanicallynotched (or nicked) by knife edge 134 as shown in FIG. 9. The knife edge134 is actuated, the wire 126 is clamped and the bond head 124 israised. The wire is pulled up and breaks at the notch or nick.

Cutting the wire 130 while it is suspended is not done in conventionalwire bonding. In conventional wire bonding, such as that used tofabricate the electrical connector of U.S. Pat. No. 4,998,885, where, asshown in FIG. 8 thereof, one end a wire is ball bonded using a wirebonded to a contact location on a substrate bent over a loop post andthe other of the wire is wedge bonded to an adjacent contact location onthe substrate. The loop is severed by a laser as shown in FIG. 6 and theends melted to form balls. This process results in adjacent contactlocations having different types of bonds, one a ball bond the other awedge bond. The spacing of the adjacent pads cannot be less than about˜20 mils because of the need to bond the wire. This spacing isunacceptable to fabricate a high density probe tip since denseintegrated circuits have pad spacing less than this amount. Incontradistinction, according to the present invention, each wire is ballbonded to adjacent contact locations which can be spaced less than 5mils apart. The wire is held tight and knife edge 134 notches the wireleaving upstanding or flying leads 120 bonded to contact locations 106in a dense array.

When the wire 130 is severed there is left on the surface 122 of pad 106an angled flying lead 120 which is bonded to surface 122 at one end andthe other end projects outwardly away from the surface. A ball can beformed on the end of the wire 130 which is not bonded to surface 122using a laser or electrical discharge to melt the end of the wire.Techniques for this are described in copending U.S. patent applicationSer. No. 07/963,346, filed Oct. 19, 1992, which is incorporated hereinby reference above.

FIG. 10 shows the wire 126 notched (or nicked) to leave wire 120disposed on surface 122 of pad 106. The wire bond head 124 is retractedupwardly as indicated by arrow 136. The wire bond head 124 has amechanism to grip and release wire 126 so that wire 126 can be tensionedagainst the shear blade to sever the wire.

After the wire bonding process is completed, a casting mold 140 as shownin FIG. 11 is disposed on surface 142 of substrate 60. The mold is atubular member of any cross-sectional shape, such as circular andpolygonal. The mold is preferably made of metal or organic materials.The length of the mold is preferably the height 144 of the wires 120. Acontrolled volume of liquid elastomer 146 is disposed into the casting140 mold and allowed to settle out (flow between the wires until thesurface is level) before curing as shown in FIG. 13. Once the elastomerhas cured, the mold is removed to provide the structure shown in FIG. 5except for cavities 112. The cured elastomer is represented by referencenumeral 44. A mold enclosing the wires 120 can be used so that theliquid elastomer can be injection molded to encase the wires 120.

The top surface of the composite polymer/wire block can be mechanicallyplanarized to provide a uniform wire height and smooth polymer surface.A moly mask with holes located over the ends of the wire contacts isused to selectively ablate (or reactive ion etch) a cup shaped recess inthe top surface of the polymer around each of the wires. The probecontacts can be reworked by repeating the last two process steps

A high compliance, high thermal stability siloxane elastomer material ispreferable for this application. The compliance of the cured elastomeris selected for the probe application. Where solder mounds are probed amore rigid elastomeric is used so that the probe tips are pushed intothe solder mounds where a gold coated aluminum pad is being probed amore compliant elastomeric material is used to permit the wires to flexunder pressure so that the probe ends in contact with the pad will moveto wipe over the pad so that good electrical contact is made therewith.The high temperature siloxane material is cast or injected and curedsimllar to other elastomeric materials. To minimize the shrinkage, theelastomer is preferably cured at lower temperature (T≦60°) followed bycomplete cure at higher temperatures (T≧80°).

Among the many commercially available elastomers, such as ECCOSIL andSYLGARD, the use of polydimethylsiloxane based rubbers best satisfy boththe material and processing requirements. However, the thermal stabilityof such elastomers is limited at temperatures below 200° C. andsignificant outgassing is observed above 100° C. We have found that thethermal stability can be significantly enhanced by the incorporation of25 wt % or more diphenylsiloxane. Further, enhancement in the thermalstability has been demonstrated by increasing the molecular weight ofthe resins (oligomers) or minimizing the cross-link junction. Theoutgassing of the elastomers can be minimized at temperatures below 300°C. by first using a thermally transient catalyst in the resin synthesisand secondly subjecting the resin to a thin film distillation to removelow molecular weight side-products. For our experiments, we have foundthat 25 wt % diphenylsiloxane is optimal, balancing the desired thermalstability with the increased viscosity associated with diphenylsiloxaneincorporation. The optimum number average molecular weight of the resinfor maximum thermal stability was found to be between 18,000 and 35,000g/mol. Higher molecular weights were difficult to cure and too viscous,once filled, to process. Network formation was achieved by a standardhydrosilylation polymerization using a hindered platinum catalyst in areactive silicon oil carrier.

In FIG. 10 when bond head 124 bonds the wire 126 to the surface 122 ofpad 106 there is formed a flattened spherical end shown as 104 in FIG.6.

The high density test probe provides a means for testing high densityand high performance integrated circuits in wafer form or as discretechips. The probe contacts can be designed for high performancefunctional testing or high temperature burn-in applications. The probecontacts can also be reworked several times by resurfacing the rigidpolymer material that encases the wires exposing the ends of thecontacts.

The high density probe contacts described in this disclosure aredesigned to be used for testing semiconductor devices in either waferform or as discrete chips. The high density probe uses metal wires thatare bonded to a rigid substrate. The wires are imbedded in a rigidpolymer that has a cup shaped recess around each to the wire ends. Thecup shaped recess 112 shown in FIG. 5 provides a positive self-aligningfunction for chips with solder ball contacts. A plurality of probe heads40 can be mounted onto a space transformation substrate 60 so that aplurality of chips can be probed an burned-in simultaneously.

An alternate embodiment of the invention would include straight wiresinstead of angled wires. Another alternate embodiment could use asuspended alignment mask for aligning the chip to the wire contactsinstead of the cup shaped recesses in the top surface of the rigidpolymer. The suspended alignment mask is made by ablating holes in athin sheet of polyimide using an excimer laser and a metal mask with thecorrect hole pattern. Another alternate embodiment of this design wouldinclude a interposer probe assembly that could be made separately fromthe test substrate as described in U.S. patent application, Ser. No.07/963,364, incorporated by reference herein above. This design could befabricated by using a copper substrate that would be etched away afterthe probe assembly is completed and the polymer is cured. This approachcould be further modified by using an adhesion de-promoter on the wiresto allow them to slide freely (along the axis of the wires) in thepolymer material.

FIG. 14 shows an alternate embodiment of probe tip 40 of FIGS. 2 and 3.As described herein above, probe tip 40 is fabricated to be originallyfixed to the surface of a first level space transformer 54. Each wire120 is wire bonded directly to a pad 106 on substrate 60 so that theprobe assembly 40 is rigidly fixed to the substrate 60. The embodimentof FIG. 14, the probe head assembly 40 can be fabricated via a discretestand alone element. This can be fabricated following the process ofU.S. patent application Ser. No. 07/963,348, filed Oct. 19, 1992, whichhas been incorporated herein by reference above. Following thisfabrication process as described herein above, wires 42 of FIG. 14 arewire bonded to a surface. Rather than being wire bonded directly to apad on a space transformation substrate, wire 42 is wire bonded to asacrificial substrate as described in the application incorporatedherein. The sacrificial substrate is removed to leave the structure ofFIG. 14. At ends 102 of wires 44 there is a flattened ball 104 caused bythe wire bond operation. In a preferred embodiment the sacrificialsubstrate to which the wires are bonded have an array of pits whichresult in a protrusion 150 which can have any predetermined shape suchas a hemisphere or a pyramid. Protrusion 150 provides a raised contactfor providing good electrical connection to a contact location againstwhich it is pressed. The clamp assembly 80 of FIGS. 2 and 3 can bemodified so that probe tip assembly 40 can be pressed towards surface 58of substrate 60 so that ends 104 of FIG. 14 can be pressed againstcontact locations such as 106 of FIG. 5 on substrate 60. Protuberances104 are aligned to pads 100 on surface 58 of FIG. 5 in a manner similarto how the conductor ends 86 and 88 of the connector in FIG. 4 arealigned to pads 75 and 64 respectively.

As shown in the process of FIGS. 7 to 9, wire 126 is ball bonded to pad106 on substrate 60. An alternative process is to start with a substrate160 as shown in FIG. 15 having contact locations 162 having anelectrically conductive material 164 disposed on surface 166 of contactlocation 162. Electrically conductive material 164 can be solder. A bondlead such as 124 of FIG. 7 can be used to dispose end 168 of wire 170against solder mound 164 which can be heated to melting. End 168 of wire170 is pressed into the molten solder mound to form wire 172 embeddedinto a solidified solder mound 174. Using this process a structuresimilar to that of FIG. 5 can be fabricated.

FIG. 16 shows another alternative embodiment of a method to fabricatethe structure of FIG. 5.

Numerals common between FIG. 15 and 16 represent the same thing. End 180elongated electrical conductor 182 is held against top surface 163 ofpad 162 on substrate 160. A beam of light 184 from laser 186 is directedat end 180 of elongated conductor 182 at the location of contact withsurface 163 of pad 162. The end 180 is laser welded to surface 163 toform protuberance 186.

In summary, the present invention is directed to high density test probefor testing high density and high performance integrated circuits inwafer form or as discrete chips. The probe contacts are designed forhigh performance functional testing and for high temperature burn inapplications. The probe is formed from an elastomeric probe tip having ahighly dense array of elongated electrical conductors embedded in anelastomeric material which is in electrical contact with a spacetransformer.

While the present invention has been described with respect to preferredembodiments, numerous modifications, changes and improvements will occurto those skilled in the art without departing from the spirit and scopeof the invention.

1. An electronic device probe for probing an electronic devicecomprising: a first space transformer having a first surface; said firstsurface having a first plurality of contact locations; a first pluralityof elongated electrical conductors each having a protuberance at one endthereof; said protuberance of each of said plurality of elongatedconductors is bonded to one of said plurality of contact locations; eachof said plurality of elongated conductors extends outwardly away fromsaid surface to form an array of elongated conductors; said array ofelongated conductors being embedded in a material; and said elongatedconductors having exposed probe tip ends at an exposed surface of saidmaterial.
 2. An electronic device probe according to claim 1, furtherincluding a second space transformer in electrical connection with saidfirst space transformer.
 3. An electronic device probe according toclaim 1, wherein said material is compliant.
 4. An electronic deviceprobe according to claim 1, wherein said material is rigid.
 5. Anelectronic device probe according to claim 1, wherein said first spacetransformer has a second surface with a second plurality of contactlocations; a second plurality of elongated conductors each in electricalcommunication with said second plurality of contact locations, each ofsaid second plurality of elongated conductors extends away from saidsecond surface.
 6. An electronic device probe according to claim 1,wherein said first space transformer has a second surface with a secondplurality of contact locations thereon and said second space transformerhas a surface with a plurality of third contact thereon.
 7. Anelectronic device probe according to claim 6, further including anelectrical interconnection means for electrically interconnecting saidsecond plurality of electrical contact locations to said third pluralityof electrical contact locations.
 8. An electronic device probe accordingto claim 7, wherein said electrical interconnection means is a pluralityof pins electrically connected to said second plurality of contactlocations said pins are adapted for insertion into a socket which iselectrically interconnected with said third plurality of contactlocations.
 9. An electronic device probe according to claim 7, whereinsaid electrical interconnection means comprises a body of elastomericmaterial having a fourth side and fifth side, a plurality of elongatedconductors extending from said fourth side to said fifth side, each ofsaid elongated conductors has a first end at said fourth side and asecond end at said fifth side, said first ends are in electrical contactwith said third plurality of contact locations and said second ends arein contact with said second plurality of contact locations.
 10. Anelectronic device probe according to claim 7, further including aholding means for holding said first space transformer in a fixedspatial relationship with respect to said second space transformer. 11.An electronic device probe according to claim 10, wherein said holdingmeans comprises an elongated member having a first end and second, saidelongated member is fixedly attached to said second space transformer atsaid first end, there being a gripping means at said second end forgripping onto said first space transformer.
 12. An electronic deviceprobe according to claim 1, further including a means for disposing saidprobe tip ends in electrical contact with contact locations on saidelectronic device.
 13. An electronic device probe according to claim 1,wherein said elastomeric material has a depression surrounding at leastone of said probe tip ends.
 14. An electronic device probe according toclaim 1, wherein said probe tip ends extend beyond said exposed surfaceof said elastomeric material.
 15. An electronic device probe accordingto claim 1, wherein said probe is part of an electronic device testtool.
 16. An electronic device probe according to claim 10, furtherincluding a means for disposing said probe tip ends in electricalcontact with contact locations on said electronic device.
 17. Anelectronic device probe according to claim 1, wherein said electronicdevice is selected from the group consisting of a semiconductor chip anda semiconductor chip packaging substrate and a semiconductor wafer. 18.An electronic device probe according to claim 1, wherein saidprotuberance is selected from the group consisting of a wire bond ballbond, a solder bump bond and a laser weld bond.
 19. An electronic deviceprobe according to claim 7, wherein said electrical interconnectionmeans is an interposer between said first space transformer and saidsecond space transformer.
 20. An electronic device probe for probing anelectronic device comprising: a first space transformer having asurface; said surface having a first plurality of contact locations; aplurality of elongated electrical conductors each having a protuberanceat one end thereof; said each of said protuberance of each of saidplurality of elongated conductors is bonded to one of said plurality ofcontact locations; each of said plurality of elongated conductorsextends outwardly away from said surface to form an array of elongatedconductors; said array of elongated conductors being embedded in anelastomeric material; said elongated conductors being embedded in anelastomeric material; a second space transformer in electricalconnection with said first space transformer; said first spacetransformer has a second surface with a second plurality of contactlocations thereon and said second space transformer has a surface with aplurality of third contact thereon; an electrical interconnection meansfor electrically interconnecting said second plurality of electricalcontact locations to said third plurality of electrical contactlocations; a holding means for holding said first space transformer in afixed spatial relationship with respect to said second spacetransformer; and a means for disposing said probe tip ends in electricalcontact with contact location on said electronic device.
 21. Anelectronic device probe according to claim 20, wherein said holdingmeans comprises an elongated member having a first end and second, saidelongated member is fixedly attached to said second space transformer atsaid first end, there being a gripping means at said second end forgripping onto said first space transformer.
 22. An electronic deviceprobe according to claim 20, wherein said elastomeric material has adepression surrounding at least one of said probe tip ends.
 23. Anelectronic device probe according to claim 20, wherein said electricalinterconnection means is an interposer between said first spacetransformer and said second space transformer.
 24. An electronic deviceprobe according to claim 1, wherein said electronic device is selectedfrom the group consisting of an integrated circuit chip, a wafer of aplurality of integrated circuit chips and a circuitized substrate. 25.An apparatus for testing or burning in an electronic device havingcontact locations comprising: a layer of elastomeric material having afirst side and a second side; a plurality of elongated electricalconductors extending from said first side to said second side; means forholding said layer; means for disposing said layer adjacent saidelectronic device so that said elongated electrical conductors are inelectrical contact with said contact locations.
 26. An apparatusaccording to claim 25, further including means selected from the groupconsisting of or applying electric current to said electronic device,voltage to said electronic device, temperature to said electronic deviceand humidity to said electronic device.
 27. A method comprising:providing an apparatus according to claim 25 and testings aid electronicdevice with said apparatus.
 28. A method comprising: providing anapparatus according to claims 26 and burning-in said electronic devicewith said apparatus.